In recent years, wireless system services such as mobile phones, wireless LAN, etc. have employed higher frequency bands, and have employed multilevel modulation or multiplexing methods using reduced spacing between carrier waves in order to increase their communication capacity. This type of wireless system often use quadrature modems, and local oscillator signals thereof are required to be of a high phase accuracy in order to secure an acceptable communications quality.
FIGS. 1A and 1B illustrate phase shifters used in commonly used radio transceivers.
FIG. 1A illustrates a quadrature demodulator used in a receiver. FIG. 1B illustrates a quadrature modulator used in a transmitter. In FIG. 1B, a received signal is amplified by a receiving amplifier 10, and is branched so as to be input into mixers 11-1 and 11-2 in the quadrature demodulator. An oscillator 15 generates a local oscillator signal, and the generated local oscillator signal is input into a phase shifter 14. In the phase shifter 14, a 0° signal, which is not phase-shifted, and a 90°-phase-shifted signal, which is phase-shifted by 90 degrees, are generated from the local oscillator signal so as to be input into the mixers 11-1 and 11-2, respectively. The received signal that is down-converted by the mixer 11-1 for receiving 0° signals is changed into an I-signal. The I-signal is passed through a low-pass filter 12-1 and an amplifier 13-1 so as to be changed into a demodulated baseband signal. Meanwhile, the received signal that is down-converted by the mixer 11-2 for receiving 90° signals is changed into a Q-signal, and is passed through a low-pass filter 12-2 and an amplifier 13-2 so as to be changed into a demodulated baseband signal.
Also in FIG. 1B, an oscillator 16 generates local oscillator signals, and a phase shifter 17 generates a 0° signal and a 90° signal to be input into mixers 20-1 and 20-2, respectively. The modulated baseband signal that is an I-signal is passed through an amplifier 18-1 and a low-pass filter 19-1 to be input into the mixer 20-1 to be up-converted, and is input into a transmitting amplifier 21. The modulated baseband signal that is a Q-signal is passed through an amplifier 18-2 and a low-pass filter 19-2 to be input into the mixer 20-2 to be up-converted, and is input into the transmitting amplifier 21. The transmitting amplifier 21 amplifies a signal obtained by synthesizing the signals that are results of the up-conversions of the I-signal and the Q-signal, and treats the resultant signal as a transmission signal.
A 0° signal and a 90° signal are generated from a local oscillation signal of a quadrature modem by using, for example, a 90° phase shifter of a dividing type. However, phase shifts caused by element processes or production variations have to be adjusted for quadrature demodulators to meet the requirement of high phase accuracy, and a 90° phase shifter needs a function of performing this adjustment.
FIGS. 2A and 2B illustrate operations of a 90° phase shifter of a dividing type.
Differential signals, i.e., a 0° signal and a 180° signal, are input to obtain a desired frequency signal with the phases being shifted by 90 degrees. Operation at the rising edge of a frequency signal two times higher, i.e., a signal with a phase shifted by 180 degrees, can produce a phase difference of 90 degrees.
As illustrated in FIG. 2A, differential signals made of a 0° signal and a 180° signal of a frequency of 2 f are used as input signals. The DC components are eliminated by a condenser. DC voltage sources 26 and 27 newly give DC components to the signals. Thereafter, the signals are input into a divider-type-90° phase shifter 25, and differential signals with phases at 0 degree and 90 degrees are obtained as output signals of frequency f.
FIG. 2B illustrates operations of a divider-type-90° phase shifter. A 0° signal and a 180° signal each having a frequency of 2 f are used as input signals. The divider-type-90° phase shifter 25 varies the signal values of the two input signals only at the rising edges of the signals so that a 0° output signal having a frequency f is obtained from a 0° input signal, and a 90° phase output signal having a frequency f is obtained from a 180° input signal.
FIGS. 3 and 4 illustrate an example of the circuit of a 90° phase shifter and its detailed configuration.
In FIG. 3, a 0° signal that was input is input into the inverted clock terminal of D latch (1) and the clock terminal of D latch (2). A 180° signal that was input is input into the clock terminal of D latch (1) and the inverted clock terminal of D latch (2). A normal output of D latch (1) is a 90° signal of the output signal, and it is input into the normal input terminal of D latch (2). An inverted output of D latch (1) is input into the inverted input terminal of D latch (2). A normal output of D latch (2) is a 0° signal of the output signal, and it is input into the inverted terminal of D latch (1). An inverted output of D latch (2) is input into the normal terminal of D latch (1).
Operations on a 0° input signal are explained. D latch (1) reads input (D) at the falling edge of (A) to output it to (B). This (B) becomes an output 90° signal. D latch (2) reads input (B) at the rising edge of (A), and outputs it to (C). This (C) becomes an output 0° signal. Accordingly, the signal value of the output 90° signal is varied at the timing of the rising edge of the input 0° signal, and the signal value of the input 0° signal is varied at the timing of the rising edge of the input 0° signal.
For the determination of the clock inputs and the inverted clock inputs in D latches (1) and (2), threshold values are set in the latches so that the individual latches input and output signals when the input clock signal exceeds the threshold value.
FIG. 4 is a timing chart for explaining the operation of the 90° phase shifter illustrated in FIG. 3.
Signal (B) is a signal output from D latch (1) that has read signal (D) at the rising edge of signal (A). Signal (C) is a signal output from D latch (2) that has read signal (B) at the rising edge of signal (A). Accordingly, the output 0° signal becomes signal (C), and the output 90° signal becomes signal (B).
FIG. 5 illustrates a conventional method of adjusting a phase in a divider-type-90° phase shifter.
The timing of the rising edge of a signal is adjusted by changing the DC voltage of the input signal so that the phase difference of an output signal is adjusted. The chart denoted by (1) in FIG. 5 represents a case of a 0° signal in which a signal is input with a lower DC voltage than the threshold voltage of the phase shifter in order to delay the timing of the point where the waveform of the input signal and the threshold value intersect. Thereby, the timing of the 0° signal can be delayed. The chart denoted by (2) in FIG. 5 illustrates a case of a 90° phase signal in which a signal is input with a higher DC voltage than the threshold voltage of the phase shifter in order to advance the timing of the point where the waveform of the input signal and the threshold value intersect. Thereby, the timing of the 90° phase signal can be advanced. Thus, the rising and falling edges are formed at the timings where the waveform of the input signal and the threshold value intersect, and accordingly, the phase difference can be reduced by implementing charts (1) and (2) in FIG. 5 at the same time in order to delay the timing of the 0° signal and advance the timing of the 90° signal. The procedures opposite to the above can increase the phase difference between the signals.
However, the range and steps of adjusting DC voltages are limited due to shifts in threshold values in phase shifters caused by element processes or production variations, or due to changes in waveforms of input signals caused by variations in speeds of transistors in the input signal circuits, and the like, and this may prevent the obtainment of a desirable phase adjustment range.
FIG. 6 illustrates a problem in a conventional technique.
As indicated by (1) in FIG. 6, in the technique of Patent Document 1, the adjustment range of DC voltages tend to be concentrated in the upper or lower side with respect to the threshold value of the phase shifter when there is a difference between the threshold voltage of the phase shifter and the DC voltage of an input signal due to the element processes or production variations, and consequently a situation occurs where the timing of the rising edge of output signals can be adjusted to be delayed to a large extent while the timing can be adjusted to be advanced only to a small extent, or vice versa. When a timing adjustment has to be made to a large extent in the direction in which an adjustment is only allowed to a small extent, the phase difference of the input signal cannot be adjusted sufficiently, which is problematic. Also, when the rising edge of the waveform of the input signal is steep as in FIG. 6, even a great change to the DC voltage of the input signal can cause only a narrow timing range of adjustment because of the steepness. Also, when a timing range of adjustment is narrow, a situation occurs where the phase difference of the output signal cannot be adjusted to the required level.
Patent Document 1:
Japanese Laid-open Patent Publication No. 58-56522